Generally, in manufacturing semiconductor devices, a desired device is manufactured by repeatedly performing various processes such as film formation, etching and the like on a semiconductor wafer. Along with the trend toward high integration and high miniaturization of the semiconductor devices, miniaturization of a line width or a hole diameter is required more and more. Further, as for a wiring material or a buried material, inexpensive Cu having a considerably low electrical resistance tends to be used to reduce the electrical resistance and deal with miniaturization of various sizes of wiring structures (Japanese Patent Application Publication No. H07-094500). Moreover, as for the wiring material or the buried material, Ta, Ti or the like tends to be used in addition to Cu.
In order to form a thin film containing the above metal, a plasma processing apparatus such as a plasma CVD apparatus, a plasma sputtering apparatus, a plasma etching apparatus or the like is generally used (see Japanese Patent Application Publication Nos. H07-094500, H09-502078, 2006-135081, and 2012-074522). In this plasma processing apparatus, an electrostatic chuck on which a semiconductor wafer is attracted and held by an electrostatic force (Coulomb force) is provided on a mounting table in a processing chamber. A plasma is generated by a high frequency power or the like in the processing chamber, and a thin film is formed on the wafer at a relatively low temperature of, e.g., about 200° C. to 400° C., by emitting metal ions from the metal target or by activating a film forming gas by the plasma thus generated. Depending on processing types, the temperature may exceed the above temperature range.
In the plasma processing, a thermal conduction gas whose pressure has been increased compared to a processing pressure is supplied between the electrostatic chuck and the wafer to improve thermal conduction between the wafer and the mounting table for control of a wafer temperature. Upon completion of the plasma processing, a floating force applied to the wafer is suppressed by stopping the supply of the thermal conduction gas and, then, a chuck voltage as an application voltage to the electrostatic chuck is off. Next, the wafer is separated from the mounting table by using lifter pins or the like.
In that case, charges remain on the wafer due to the effect of electrostatic attraction, so that the remaining charges need to be removed to prevent adhesion of particles or bounce of the wafer during the separation of the wafer. Therefore, conventionally, an opposite voltage is applied to an electrostatic chuck (Japanese Patent Application Publication No. H07-094500). In addition, an optimal voltage for minimizing an electrostatic attraction force is applied, or a charge neutralization gas is supplied (Japanese Patent Application Publication No. 2006-135081).
Meanwhile, it is general to increase a chuck voltage in order to sufficiently increase an attraction force during the plasma processing. However, when a sufficient attraction force is obtained, residual charges cannot be sufficiently removed even by the aforementioned various charge neutralization processes. This causes generation of particles when the wafer is separated from the mounting table.
Particularly, the amount of remaining charges is increased in proportion to the chuck voltage, so that the relationship between the attraction force and the amount of generated particles is a trade-off relationship. Therefore, it is currently required to develop a new method for suppressing the particle generation amount while realizing a sufficient attraction force.